— G 5 and G 6 performance considerations

The CMOS-based IBM S/390 Parallel Enterprise Servers have always employed the technique of memory caching to bridge the gap between processor speed and mainmemory access time. However, that gap has widened with each succeeding system generation, requiring increasingly sophisticated, multiple-level cache structures in order to minimize memory-access latency. The IBM S/390 G5 and G6 include two-level caching, with a binodal second-level cache. This paper reviews the principles of cache design, discusses the performance requirements of S/390 relative to caching, and describes how those requirements are addressed by the binodal L2 cache in the G5 and G6 systems.